Journal Information
Research Areas
Publication Ethics and Malpractice Statement
To Scholarlink Resource Center
Guidelines for Authors
For Authors
Instructions to Authors
Copyright forms
Submit Manuscript
Call for papers
Guidelines for Reviewers
For Reviewers
Review Forms
Contacts and Support
Support and Contact
List of Issues


Journal of Emerging Trends in Engineering and Applied Sciences (JETEAS)


Article Title: Cache Architecture Limitations in Multicore Processors
by Wael Mohamed, Maher Mansour Abd El-Aziz

Today supercomputers play a big role in our life for complex applications. Multicore processors represent the most significant part in supercomputers. A multicore processor consists of several cores which can execute different tasks independently. Due to the budget and chip area limit, the last level cache is usually shared among cores. Running tasks on different cores access the shared cache intensively and concurrently. This may lead to cache miss rate and significant performance degradation. In this paper, we study the effect of cache architectures on the performance of multicore processors for multi-threading applications and their limitations on increasing the number of processor cores. The study focus on two design issues: cache architecture and configuration parameters. It also based on a cache simulator that models the functionality of a multicore cache hierarchy with arbitrary levels and various organizations. Our evaluations also help in determining the best cache architecture and configuration for a given number of cores to obtain the good performance.
Keywords: cache memory, multicore processing, performance analysis, simulation architecture
Download full paper

ISSN: 2141-7016

Editor in Chief.

Prof. Gui Yun Tian
Professor of Sensor Technologies
School of Electrical, Electronic and Computer Engineering
University of Newcastle
United Kingdom



Copyright © Journal of Emerging Trends in Engineering and Applied Sciences 2010